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Lars-Peter Clausen
7f40e120c8
SystemVerilog allows to completely omit the `parameter` or `localparam` keyword in the parameter list. Both at the beginning and before redefining the parameter data type. This is not support in Verilog. Add regression tests that check that this is supported when in SystemVerilog mode. It is not valid to use an implicit data type e.g. just `signed` when `parameter` was omitted, add regression tests to check for this as well. Signed-off-by: Lars-Peter Clausen <[email protected]>
31 lines
595 B
Verilog
31 lines
595 B
Verilog
// Check that all parameters in a parameter port list after a `localparam` get
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// elaborated as localparams, until the next `parameter`. Check that this is the
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// case even when the data type of the parameter is redefined.
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module a #(
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parameter A = 1, B = 2,
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localparam C = 3, real D = 4,
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parameter E = 5
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);
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initial begin
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if (A == 10 && B == 20 && C == 3 && D == 4 && E == 50) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module b;
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a #(
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.A(10),
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.B(20),
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.D(40), // This will cause an error
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.E(50)
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) i_a();
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endmodule
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