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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
70 lines
1.2 KiB
Verilog
70 lines
1.2 KiB
Verilog
module main;
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reg [7:0] th2, init;
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reg carry, clk, rst, foo;
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(* ivl_synthesis_on *)
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always @(posedge clk) begin
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if (rst) begin
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th2 <= 0;
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carry <= 1;
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foo <= 0; // This causes foo to be an output to the block.
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end else begin
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if (carry)
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{carry, th2} <= {1'b0, init};
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else
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{carry, th2} <= {1'b0, th2} + 9'h1;
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end
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end
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(* ivl_synthesis_off *)
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initial begin
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rst = 1;
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clk = 0;
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init = 8'hfe;
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$monitor("clk=%b: rst=%b, th2=%h, carry=%b", clk, rst, th2, carry);
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 0) begin
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$display("FAILED -- foo=%b", foo);
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$finish;
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end
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rst = 0;
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#1 clk = 1;
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#1 clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (th2 !== 8'hff) begin
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$display("FAILED -- th2=%h (1)", th2);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (th2 !== 8'h00) begin
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$display("FAILED == th2=%h", th2);
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$finish;
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end
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if (carry !== 1) begin
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$display("FAILED -- carry=%b, th2=%h", carry, th2);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (th2 !== 8'hfe) begin
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$display("FAILED -- th2=%h", th2);
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$finish;
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end
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#1 $strobe("PASSED");
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end // initial begin
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endmodule // main
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