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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
/*
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* This tests the latching of an output that isn't really an output,
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* but an intermediate symbol that is only used in some clauses.
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*/
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module main;
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reg [15:0] out, a;
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reg [7:0] b;
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reg cy;
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reg with_carry;
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(* ivl_combinational *)
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always @(with_carry, a, b, cy)
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if (with_carry) begin
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{cy, out[7:0]} = {1'b0, a[7:0]} + {1'b0, b[7:0]};
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out[15:8] = a[15:8] + {7'b0, cy};
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end else begin
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out = a + {8'h00, b};
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end
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(* ivl_synthesis_off *)
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initial begin
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a = 16'h00fe;
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b = 8'h00;
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with_carry = 0;
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#1 if (out !== 16'h00fe) begin
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$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
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$finish;
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end
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with_carry = 1;
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#1 if (out !== 16'h00fe) begin
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$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
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$finish;
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end
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b = 2;
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#1 if (out !== 16'h0100) begin
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$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
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$finish;
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end
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with_carry = 0;
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#1 if (out !== 16'h0100) begin
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$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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