mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-04 08:34:09 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
176 lines
7.5 KiB
Verilog
176 lines
7.5 KiB
Verilog
// Test implicit casts during task input assignments.
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module implicit_cast();
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real src_r;
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bit unsigned [7:0] src_u2;
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bit signed [7:0] src_s2;
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logic unsigned [7:0] src_u4;
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logic signed [7:0] src_s4;
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logic unsigned [7:0] src_ux;
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logic signed [7:0] src_sx;
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real dst_r;
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bit unsigned [3:0] dst_u2s;
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bit signed [3:0] dst_s2s;
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bit unsigned [11:0] dst_u2l;
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bit signed [11:0] dst_s2l;
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logic unsigned [3:0] dst_u4s;
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logic signed [3:0] dst_s4s;
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logic unsigned [11:0] dst_u4l;
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logic signed [11:0] dst_s4l;
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task cp_r(output real dst,
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input real src);
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dst = src;
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endtask
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task cp_u2s(output bit unsigned [3:0] dst,
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input bit unsigned [3:0] src);
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dst = src;
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endtask
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task cp_s2s(output bit signed [3:0] dst,
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input bit signed [3:0] src);
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dst = src;
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endtask
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task cp_u2l(output bit unsigned [11:0] dst,
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input bit unsigned [11:0] src);
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dst = src;
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endtask
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task cp_s2l(output bit signed [11:0] dst,
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input bit signed [11:0] src);
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dst = src;
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endtask
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task cp_u4s(output logic unsigned [3:0] dst,
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input logic unsigned [3:0] src);
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dst = src;
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endtask
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task cp_s4s(output logic signed [3:0] dst,
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input logic signed [3:0] src);
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dst = src;
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endtask
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task cp_u4l(output logic unsigned [11:0] dst,
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input logic unsigned [11:0] src);
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dst = src;
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endtask
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task cp_s4l(output logic signed [11:0] dst,
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input logic signed [11:0] src);
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dst = src;
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endtask
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bit failed;
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initial begin
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failed = 0;
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src_r = -7;
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src_u2 = 7;
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src_s2 = -7;
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src_u4 = 7;
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src_s4 = -7;
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src_ux = 8'bx0z00111;
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src_sx = 8'bx0z00111;
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$display("cast to real");
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cp_r(dst_r, src_r); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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cp_r(dst_r, src_u2); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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cp_r(dst_r, src_s2); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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cp_r(dst_r, src_u4); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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cp_r(dst_r, src_s4); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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cp_r(dst_r, src_ux); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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cp_r(dst_r, src_sx); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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$display("cast to small unsigned bit");
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cp_u2s(dst_u2s, src_r); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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cp_u2s(dst_u2s, src_u2); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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cp_u2s(dst_u2s, src_s2); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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cp_u2s(dst_u2s, src_u4); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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cp_u2s(dst_u2s, src_s4); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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cp_u2s(dst_u2s, src_ux); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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cp_u2s(dst_u2s, src_sx); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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$display("cast to small signed bit");
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cp_s2s(dst_s2s, src_r); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_u2); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_s2); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_u4); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_s4); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_ux); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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cp_s2s(dst_s2s, src_sx); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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$display("cast to large unsigned bit");
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cp_u2l(dst_u2l, src_r); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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cp_u2l(dst_u2l, src_u2); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
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cp_u2l(dst_u2l, src_s2); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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cp_u2l(dst_u2l, src_u4); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
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cp_u2l(dst_u2l, src_s4); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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cp_u2l(dst_u2l, src_ux); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
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cp_u2l(dst_u2l, src_sx); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
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$display("cast to large signed bit");
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cp_s2l(dst_s2l, src_r); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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cp_s2l(dst_s2l, src_u2); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
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cp_s2l(dst_s2l, src_s2); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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cp_s2l(dst_s2l, src_u4); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
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cp_s2l(dst_s2l, src_s4); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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cp_s2l(dst_s2l, src_ux); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
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cp_s2l(dst_s2l, src_sx); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
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$display("cast to small unsigned logic");
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cp_u4s(dst_u4s, src_r); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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cp_u4s(dst_u4s, src_u2); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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cp_u4s(dst_u4s, src_s2); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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cp_u4s(dst_u4s, src_u4); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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cp_u4s(dst_u4s, src_s4); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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cp_u4s(dst_u4s, src_ux); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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cp_u4s(dst_u4s, src_sx); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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$display("cast to small signed logic");
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cp_s4s(dst_s4s, src_r); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_u2); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_s2); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_u4); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_s4); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_ux); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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cp_s4s(dst_s4s, src_sx); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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$display("cast to large unsigned logic");
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cp_u4l(dst_u4l, src_r); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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cp_u4l(dst_u4l, src_u2); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
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cp_u4l(dst_u4l, src_s2); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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cp_u4l(dst_u4l, src_u4); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
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cp_u4l(dst_u4l, src_s4); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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cp_u4l(dst_u4l, src_ux); $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
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cp_u4l(dst_u4l, src_sx); $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
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$display("cast to large signed logic");
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cp_s4l(dst_s4l, src_r); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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cp_s4l(dst_s4l, src_u2); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
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cp_s4l(dst_s4l, src_s2); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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cp_s4l(dst_s4l, src_u4); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
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cp_s4l(dst_s4l, src_s4); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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cp_s4l(dst_s4l, src_ux); $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
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cp_s4l(dst_s4l, src_sx); $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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