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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
41 lines
895 B
Verilog
41 lines
895 B
Verilog
/*
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* From PR#379
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*/
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`define IDLE 2'b00
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`define COUNT 2'b01
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`define DONE 2'b10
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module Counter56 (POR, CLK, VoltageOK, ChargeDone );
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input POR;
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input CLK;
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input VoltageOK;
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output ChargeDone;
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reg [1:0] CounterState, nextCounterState;
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wire [8:0] nextMinuteCounter;
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always @(posedge CLK or negedge POR)
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if (!POR)
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CounterState = 2'b00;
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else
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CounterState = nextCounterState;
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always @(VoltageOK or CounterReset) // CounterReset should make an error
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casez (CounterState)
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`IDLE: begin
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nextCounterState = (VoltageOK) ? `COUNT : `IDLE;
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end
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`COUNT: begin
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nextCounterState = (VoltageOK) ? `COUNT : `IDLE;
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end
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`DONE: begin
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nextCounterState = `DONE;
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end
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default: begin
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nextCounterState = 2'bxx;
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end
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endcase
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endmodule
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