mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 03:03:08 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
41 lines
916 B
Verilog
41 lines
916 B
Verilog
/*
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* This is a simple test of a generate loop.
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*/
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module main;
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parameter SIZE = 4;
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wire [SIZE:0] cin;
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reg [SIZE-1:0] a, b;
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wire [SIZE-1:0] q;
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// This generates a ripple adder by using a generate loop to
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// instantiate an array of half-adders.
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genvar i;
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assign cin[0] = 0;
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for (i=0 ; i<SIZE ; i = i+1) begin : slice
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wire [1:0] sum = a[i] + b[i] + cin[i];
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assign q[i] = sum[0];
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assign cin[i+1] = sum[1];
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end
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wire [SIZE:0] total = {cin[SIZE], q};
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// Test the ripple adder by finding all the possible sums.
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reg [2*SIZE:0] idx;
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initial begin
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for (idx = 0 ; idx < (1<<(2*SIZE)) ; idx = idx+1) begin
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a = idx[ SIZE-1: 0];
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b = idx[2*SIZE-1:SIZE];
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#1 if (total !== a+b) begin
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$display("FAILED -- total=%b, a=%b, b=%b", total, a, b);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule
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