mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 01:33:07 +02:00
Lars-Peter Clausen
b37636e4fc
Check that the following declarations inside a generate block generate an error: * module, program or interface * specparam * specify block * timeunit Signed-off-by: Lars-Peter Clausen <[email protected]>
18 lines
235 B
Verilog
18 lines
235 B
Verilog
// Check that declaring a specparam inside a generate block is an error
|
|
|
|
module test #(
|
|
parameter A = 1
|
|
);
|
|
|
|
generate
|
|
if (A) begin
|
|
specparam x = 10; // Error
|
|
end
|
|
endgenerate
|
|
|
|
initial begin
|
|
$display("FAILED");
|
|
end
|
|
|
|
endmodule
|