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Lars-Peter Clausen
b37636e4fc
Check that the following declarations inside a generate block generate an error: * module, program or interface * specparam * specify block * timeunit Signed-off-by: Lars-Peter Clausen <[email protected]>
17 lines
239 B
Verilog
17 lines
239 B
Verilog
// Check that declaring a module inside a generate block is an error
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module test #(
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parameter A = 1
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);
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generate
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if (A) begin
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// Error
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module inner;
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initial $display("FAILED");
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endmodule
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end
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endgenerate
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endmodule
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