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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
31 lines
540 B
Verilog
31 lines
540 B
Verilog
module main;
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parameter COND = 1;
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parameter SEL = 0;
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parameter VAL0 = 0;
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parameter VAL1 = 1;
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parameter VAL2 = 2;
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wire [3:0] foo;
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if (COND) begin
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case (SEL)
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0: assign foo = VAL0;
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1: assign foo = VAL1;
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2: assign foo = VAL2;
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endcase // case (SEL)
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end else begin
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assign foo = 'bx;
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end
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initial begin
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#1 $display("foo = %b", foo);
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if (foo !== VAL0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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