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Check that statements that are not allowed in functions or final procedures are still rejected when they are placed in a named block scope. Signed-off-by: Lars-Peter Clausen <[email protected]>
22 lines
292 B
Verilog
22 lines
292 B
Verilog
// Check that function context is preserved when elaborating nested blocks.
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module test;
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reg x;
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integer y;
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function integer f;
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input a;
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begin : nested
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x <= a;
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f = 0;
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end
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endfunction
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initial begin
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y = f(1'b1);
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$display("FAILED");
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end
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endmodule
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