mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 06:43:22 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
64 lines
1.1 KiB
Verilog
64 lines
1.1 KiB
Verilog
module static test();
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function integer accumulate1(input integer value);
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begin:blk
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static int acc = 1;
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acc = acc + value;
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return acc;
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end
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endfunction
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function automatic integer accumulate2(input integer value);
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begin:blk
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automatic int acc = 1;
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acc = acc + value;
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return acc;
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end
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endfunction
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localparam value1 = accumulate1(2);
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localparam value2 = accumulate1(3);
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localparam value3 = accumulate2(2);
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localparam value4 = accumulate2(3);
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integer value;
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initial begin
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static reg failed = 0;
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$display("%d", value1);
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if (value1 !== 3) failed = 1;
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$display("%d", value2);
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if (value2 !== 4) failed = 1;
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$display("%d", value3);
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if (value3 !== 3) failed = 1;
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$display("%d", value4);
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if (value4 !== 4) failed = 1;
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value = accumulate1(2);
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$display("%d", value);
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if (value !== 3) failed = 1;
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value = accumulate1(3);
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$display("%d", value);
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if (value !== 6) failed = 1;
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value = accumulate2(2);
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$display("%d", value);
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if (value !== 3) failed = 1;
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value = accumulate2(3);
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$display("%d", value);
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if (value !== 4) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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