mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:03:32 +02:00
Lars-Peter Clausen
fe5e60840f
Check that function calls with empty arguments are supported. Check the general case and special cases such as calling a function with empty arguments as part of a module port binding or force statements in automatic contexts. Also check that calling a function with too many trailing empty arguments as well as passing an empty argument for a port without a default value is an error. Signed-off-by: Lars-Peter Clausen <[email protected]>
17 lines
355 B
Verilog
17 lines
355 B
Verilog
// Check that an error is reported when passing an empty function argument for a
|
|
// port without a default value.
|
|
|
|
module test;
|
|
|
|
function f(integer a, integer b = 2);
|
|
return a + 10 * b + 100 * c;
|
|
endfunction
|
|
|
|
initial begin
|
|
integer x;
|
|
x = f( , 3); // This should fail. No default value specified.
|
|
$display("FAILED");
|
|
end
|
|
|
|
endmodule
|