Files
iverilog/ivtest/ivltests/func_empty_arg3.v
T
Lars-Peter Clausen fe5e60840f Add regression test for function calls with empty arguments
Check that function calls with empty arguments are supported. Check the
general case and special cases such as calling a function with empty
arguments as part of a module port binding or force statements in automatic
contexts.

Also check that calling a function with too many trailing empty arguments
as well as passing an empty argument for a port without a default value is
an error.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2023-01-16 08:07:03 -08:00

42 lines
863 B
Verilog

// Check that it is possible to call functins with empty arguments if they have
// default values. Check that this works if the function call is part of a force
// statement in an automatic context.
module test;
bit failed = 1'b0;
`define check(expr, val) \
if (expr !== val) begin \
$display("FAILED. %s, expected %d, got %d", `"expr`", val, expr); \
failed = 1'b1; \
end
integer x, y, z, w;
function automatic integer f(integer a = 1, integer b = 2, integer c = 3);
return a * 100 + b * 10 + c;
endfunction
task automatic t;
force x = f(4, , 6);
force y = f(4, 5, );
force z = f(4, , );
force w = f( , , 6);
endtask
initial begin
t;
`check(x, 426);
`check(y, 453);
`check(z, 423);
`check(w, 126);
if (!failed) begin
$display("PASSED");
end
end
endmodule