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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
54 lines
1.0 KiB
Verilog
54 lines
1.0 KiB
Verilog
/* fopen2 - test $fopen and $fclose system tasks */
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module fopen2;
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integer fp1, fp2, fp3, fp4;
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integer dfp;
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reg error;
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reg [31:0] foo;
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initial begin
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error = 0;
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fp1 = $fopen("work/fopen2.out1");
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checkfp(fp1);
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dfp = fp1|1;
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$fdisplay(dfp, "fp1=%d", fp1);
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fp2 = $fopen("work/fopen2.out2");
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checkfp(fp2);
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dfp = fp2|1;
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$fdisplay(dfp, "fp2=%d", fp2);
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fp3 = $fopen("work/fopen2.out3");
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checkfp(fp3);
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dfp = fp3|1;
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$fdisplay(dfp, "fp3=%d", fp3);
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$fclose(fp2);
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fp4 = $fopen("work/fopen2.out4");
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checkfp(fp4);
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dfp = fp4|1;
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$fdisplay(dfp, "fp4=%d", fp4);
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$fclose(fp1);
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$fclose(fp2);
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$fclose(fp3);
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$fclose(fp4);
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if(error == 0)
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$display("PASSED");
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end // initial begin
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task checkfp;
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input [31:0] fp;
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begin
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if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) begin
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$display("FAILED fopen fp=%d", fp);
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error = 1;
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end
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end
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endtask // checkfp
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endmodule
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