mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 06:33:02 +02:00
Lars-Peter Clausen
7973b105ac
Check that sub-blocks containing variables inside of `final` procedures do get executed. Signed-off-by: Lars-Peter Clausen <[email protected]>
21 lines
324 B
Verilog
21 lines
324 B
Verilog
// Check that sub-blocks with variable declarations inside final procedures get
|
|
// executed
|
|
|
|
|
|
module test;
|
|
|
|
final begin
|
|
static int x = -1;
|
|
for (int i = 0; i < 1; i++) begin
|
|
x = i;
|
|
end
|
|
|
|
if (x === 0) begin
|
|
$display("PASSED");
|
|
end else begin
|
|
$display("FAILED");
|
|
end
|
|
end
|
|
|
|
endmodule
|