mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
119 lines
3.1 KiB
Verilog
119 lines
3.1 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This test tests simple zero-extend of small r-values into large
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* l-values.
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*
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* Correction and extensions by EML; 2007-11-15
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*/
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module main;
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reg [3:0] y;
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reg signed xs;
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reg x;
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reg fail;
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initial begin
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fail = 0;
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x = 1'b0;
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y = x;
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if (y !== 4'b0000) begin
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$display("FAILED 1 -- x=%b, y=%b", x, y);
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fail = 1;
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end
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x = 1'b1;
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y = x;
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if (y !== 4'b0001) begin
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$display("FAILED 2 -- x=%b, y=%b", x, y);
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fail = 1;
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end
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// x is a 1-bit unsigned reg; it zero-extends when assigned to y
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x = 1'bx;
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y = x;
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if (y !== 4'b000x) begin
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$display("FAILED 3 -- x=%b, y=%b", x, y);
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fail = 1;
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end
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// x is a 1-bit unsigned reg; it zero-extends when assigned to y
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x = 1'bz;
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y = x;
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if (y !== 4'b000z) begin
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$display("FAILED 4 -- x=%b, y=%b", x, y);
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fail = 1;
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end
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// xs is a 1-bit signed reg; it top-bit-extends when assigned to y
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xs = 1'bx;
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y = xs;
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if (y !== 4'bxxxx) begin
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$display("FAILED 5 -- xs=%b, y=%b", xs, y);
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fail = 1;
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end
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// xs is a 1-bit signed reg; it top-bit-extends when assigned to y
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xs = 1'bz;
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y = xs;
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if (y !== 4'bzzzz) begin
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$display("FAILED 6 -- xs=%b, y=%b", xs, y);
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fail = 1;
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end
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// 'bx is an unsized unsigned constant; it X-extends to the size of
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// the expression it is in
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y = 'bx;
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if (y !== 4'bxxxx) begin
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$display("FAILED 7 -- y=%b", y);
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fail = 1;
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end
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// 'bz is an unsized unsigned constant; it Z-extends to the size of
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// the expression it is in
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y = 'bz;
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if (y !== 4'bzzzz) begin
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$display("FAILED 8 -- y=%b", y);
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fail = 1;
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end
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// this is the only case in which a constant pads to the left with
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// X's. 4'bx is 4-bit unsigned, but it is specified with fewer than 4
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// bits
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y = 4'bx;
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if (y !== 4'bxxxx) begin
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$display("FAILED 9 -- y=%b", y);
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fail = 1;
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end
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// this is the only case in which a constant pads to the left with
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// Z's. 4'bz is 4-bit unsigned, but it is specified with fewer than 4
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// bits
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y = 4'bz;
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if (y !== 4'bzzzz) begin
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$display("FAILED 10 -- y=%b", y);
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fail = 1;
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end
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if (!fail) $display("PASSED");
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end // initial begin
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endmodule // main
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