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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
34 lines
713 B
Verilog
34 lines
713 B
Verilog
// Trigger breakage of Icarus Verilog CVS 2004-06-18
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// $ iverilog netnet.v
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// netnet.v:7: internal error: pin(3) out of bounds(3)
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// netnet.v:7: : typeid=6NetNet
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// ivl: netlist.cc:208: Link &NetObj::pin (unsigned int): Assertion `idx < npins_' failed.
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// $
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// Larry Doolittle <[email protected]>
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`timescale 1ns / 1ns
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module netnet();
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reg [2:0] s;
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wire s_ones;
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assign s_ones = (s==7);
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initial begin
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s = 3'b111;
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#1 if (s_ones !== 1) begin
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$display("FAILED -- %b==7 returns %b", s, s_ones);
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$finish;
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end
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s = 3'b011;
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#1 if (s_ones !== 0) begin
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$display("FAILED -- %b==7 returns %b", s, s_ones);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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