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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
78 lines
2.1 KiB
VHDL
78 lines
2.1 KiB
VHDL
------------------------------------------------------------------------------
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-- Author: Oswaldo Cadenas
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-- Date: September 27 2011
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--
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-- Summary: This system runs an internal counter 0,1,2, ..., 7, 0, 1,
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-- and also accepts an enable signal
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-- it generates an output y (4 bits) as:
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-- if (e = 0) y = 0000
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-- if (e = 1) then
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-- y = 1000 when counter is 0
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-- y = 0100 when counter is 1
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-- y = 0010 when counter is 2
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-- y = 0001 when counter is 3
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-- y = 1111 other count
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-- internaly the design uses some enumartion arguments for decoding and encoding
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity enumsystem is
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port (clk, reset: in std_logic;
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en: in std_logic; -- enable
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y: out std_logic_vector (0 to 3) ); -- decoded output
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end enumsystem;
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architecture enumsystem_rtl of enumsystem is
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type States is (zero, one, two, three, other);
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signal mystate: States;
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signal Counter: std_logic_vector (2 downto 0);
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begin
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SmallCounter : process (clk, reset)
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begin
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if ( clk'event and clk = '1') then
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if (reset = '1') then
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Counter <= (others => '0');
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else
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Counter <= Counter + 1;
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end if;
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end if;
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end process;
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encoding_process: process (Counter)
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begin
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case Counter is
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when "000" => mystate <= zero;
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when "001" => mystate <= one;
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when "010" => mystate <= two;
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when "011" => mystate <= three;
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when others => mystate <= other;
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end case;
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end process;
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decoding_process: process (mystate, en)
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begin
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if (en = '1') then
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case mystate is
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when zero => y <= "1000";
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when one => y <= "0100";
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when two => y <= "0010";
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when three => y <= "0001";
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when others => y <= "1111";
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end case;
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else
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y <= "0000";
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end if;
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end process;
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end enumsystem_rtl;
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