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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 03:03:08 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
42 lines
785 B
Verilog
42 lines
785 B
Verilog
/*
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* This program tests that enumeration values work and are
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* implicitly translated to integer values.
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*/
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module main;
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enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET,
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BLACK = 10, WHITE = 'd11
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} color1;
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int var1;
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initial begin
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color1 = RED;
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var1 = RED;
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$display("color1 = %0d, var1 = %0d", color1, var1);
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if (color1 !== 0) begin
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$display("FAILED");
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$finish;
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end
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if (var1 !== 0) begin
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$display("FAILED");
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$finish;
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end
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color1 = GREEN;
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var1 = GREEN;
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$display("color1 = %0d, var1 = %0d", color1, var1);
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if (color1 !== 3) begin
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$display("FAILED");
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$finish;
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end
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if (var1 !== 3) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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