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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
10 lines
281 B
Verilog
10 lines
281 B
Verilog
module top;
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// This should be okay because the size matches.
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enum reg[3:0] {VAL1, XX1=4'bxxxx} en1;
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// But these should fail because the size is wrong.
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enum reg[3:0] {VAL2, XX2=3'bxxx} en2;
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enum reg[3:0] {VAL3, XX3=5'bxxxxx} en3;
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initial $display("FAILED");
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endmodule
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