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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
/*
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* This program tests that enumeration value first/last/next
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* methods work properly. The .next method requires some run-time
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* support for enumeration.
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*/
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module main;
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enum { RED, GREEN = 2, BLUE } color1;
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initial begin
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color1 = RED;
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$display("color1.first == %0d", color1.first);
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$display("color1.last == %0d", color1.last);
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$display("color1.num == %0d", color1.num);
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$display("color1.next == %0d", color1.next);
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color1 = color1.next;
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if (color1 != GREEN || color1 !== 2) begin
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$display("FAILED -- should be %0d, got %0d", GREEN, color1);
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$finish;
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end
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color1 = color1.next;
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if (color1 != BLUE || color1 !== 3 || color1 != color1.last) begin
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$display("FAILED -- should be %0d, got %0d", BLUE, color1);
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$finish;
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end
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color1 = color1.prev;
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if (color1 != GREEN || color1 !== 2) begin
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$display("FAILED -- should be %0d, got %0d", GREEN, color1);
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$finish;
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end
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color1 = color1.prev;
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if (color1 != RED || color1 !== 0 || color1 != color1.first) begin
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$display("FAILED -- should be %0d, got %0d", RED, color1);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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