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Lars-Peter Clausen
0c123b8498
Check that the signedness of the return value of methods is handled correctly. * When sign extending * When passing as a value to a system function Check this for both methods on user defined class as well as built-in methods on SystemVerilog types. Signed-off-by: Lars-Peter Clausen <[email protected]>
36 lines
714 B
Verilog
36 lines
714 B
Verilog
// Check that the signedness of methods on the built-in enum type is handled
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// correctly when calling the function without parenthesis and passing the
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// result to a system function.
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module test;
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enum shortint {
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A = -1,
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B = -2,
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C = -3
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} es;
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enum bit [15:0] {
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X = 65535,
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Y = 65534,
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Z = 65533
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} eu;
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string s;
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initial begin
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es = B;
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eu = Y;
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s = $sformatf("%0d %0d %0d %0d %0d %0d %0d %0d",
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es.first, es.last, es.prev, es.next,
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eu.first, eu.last, eu.prev, eu.next);
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if (s == "-1 -3 -1 -3 65535 65533 65535 65533") begin
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$display("PASSED");
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end else begin
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$display("FAILED s=%s", s);
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end
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end
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endmodule
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