mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
51 lines
494 B
Verilog
51 lines
494 B
Verilog
// Check that all sorts of enum dimension declarations are handled correctly and
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// do not cause an assert or segfault.
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module test;
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// These are invalid
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enum logic [$] {
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A
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} a;
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enum logic [] {
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B
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} b;
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enum logic [-1] {
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C
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} c;
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enum logic [0] {
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D
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} d;
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enum logic [1:0][3:0] {
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E
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} e;
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// These are valid
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enum logic [0:2] {
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F
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} f;
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enum logic [2:0] {
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G
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} g;
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enum logic [-1:-2] {
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H
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} h;
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// These are valid as an extension in iverilog
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enum logic [16] {
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I
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} i;
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int x;
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endmodule
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