mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 01:56:52 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
109 lines
1.9 KiB
Verilog
109 lines
1.9 KiB
Verilog
module top;
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reg passed;
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reg pevt;
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reg evt;
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reg pedge;
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reg nedge;
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initial begin
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passed = 1'b1;
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#1; // Check X to 0
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{pedge, nedge} = 2'b01;
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evt = 1'b0;
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#1; // Check 0 to X
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'bx;
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#1; // Check X to 1
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'b1;
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#1; // Check 1 to X
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pevt = evt;
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{pedge, nedge} = 2'b01;
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evt = 1'bx;
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#1; // Check X to Z
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pevt = evt;
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{pedge, nedge} = 2'b00;
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evt = 1'bz;
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#1; // Check Z to X
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pevt = evt;
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{pedge, nedge} = 2'b00;
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evt = 1'bx;
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#1; // Check X to Z (again)
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pevt = evt;
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{pedge, nedge} = 2'b00;
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evt = 1'bz;
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#1; // Check Z to 0
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pevt = evt;
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{pedge, nedge} = 2'b01;
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evt = 1'b0;
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#1; // Check 0 to Z
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'bz;
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#1; // Check Z to 1
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'b1;
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#1; // Check 1 to Z
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pevt = evt;
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{pedge, nedge} = 2'b01;
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evt = 1'bz;
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#1; // Check Z to 1 (again)
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'b1;
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#1; // Check 1 to 0
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pevt = evt;
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{pedge, nedge} = 2'b01;
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evt = 1'b0;
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#1; // Check 0 to 1
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pevt = evt;
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{pedge, nedge} = 2'b10;
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evt = 1'b1;
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#1;
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if (passed) $display("PASSED");
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end
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always @(posedge evt) begin
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if (!pedge) begin
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$display("Error: posedge detected for %b -> %b", pevt, evt);
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passed = 1'b0;
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end
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end
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always @(negedge evt) begin
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if (!nedge) begin
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$display("Error: negedge detected for %b -> %b", pevt, evt);
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passed = 1'b0;
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end
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end
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always @(edge evt) begin
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if (!nedge && !pedge) begin
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$display("Error: edge detected for %b -> %b", pevt, evt);
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passed = 1'b0;
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end
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end
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always @(evt)
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$display("Checking the %b -> %b event", pevt, evt);
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endmodule
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