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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
749 B
Verilog
30 lines
749 B
Verilog
module main;
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typedef struct packed {
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logic [7:0] high;
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logic [7:0] low;
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} word;
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word [2] array; // word[0:1] exposes the bug as well
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word single;
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initial begin
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array[0].high = "a";
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array[0].low = "b";
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array[1].high = "c";
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array[1].low = "d";
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$display("%s", array[0]); // good
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$display("%s %s", array[0].high, array[0].low);
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$display("%s", array[1]); // good
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// the line below displays contents of array[0] instead of array[1]
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$display("%s %s", array[1].high, array[1].low);
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// below everything is fine
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single = array[0];
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$display("%s", single);
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$display("%s %s", single.high, single.low);
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end
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endmodule
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