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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
32 lines
422 B
Verilog
32 lines
422 B
Verilog
module bug();
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reg clock = 0;
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always begin
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#1 clock = 1;
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#1 clock = 0;
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end
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integer count = 0;
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initial begin:counter
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forever begin
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repeat (2) @(posedge clock);
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count = count + 1;
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$display(count);
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end
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end
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initial begin
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repeat (5) @(posedge clock);
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disable counter;
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repeat (4) @(posedge clock);
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if (count === 2)
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$display("PASSED");
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else
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$display("FAILED");
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$finish;
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end
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endmodule
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