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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
508 B
Verilog
30 lines
508 B
Verilog
// This test is mostly to make sure valgrind cleans up correctly.
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`timescale 1ns/1ns
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module top;
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wire real rtm;
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wire [31:0] res1, res2;
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integer a = 10;
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assign #1 rtm = $realtime;
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assign #1 res1 = $clog2(a);
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lwr dut(res2, a);
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initial begin
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$monitor($realtime,, rtm, res1,, res2,, a);
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#5 a = 20;
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end
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endmodule
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module lwr(out, in);
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output [31:0] out;
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input [31:0] in;
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wire [31:0] out, in;
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assign out = $clog2(in);
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specify
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(in => out) = (1, 1);
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endspecify
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endmodule
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