mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 04:33:56 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
78 lines
1.3 KiB
Verilog
78 lines
1.3 KiB
Verilog
`timescale 1ns/100ps
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module assign_test;
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reg clk;
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reg cat1;
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reg cat2;
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reg cat3;
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reg cat4;
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reg foo1;
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reg foo2;
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reg foo3;
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reg foo4;
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reg bar1;
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reg bar2;
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reg bar3;
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reg bar4;
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initial begin
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clk = 0;
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#100 $finish(0);
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end
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always begin
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clk = 0;
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#50;
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clk = 1;
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#50;
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end
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always @(posedge clk) begin
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cat1 = #1 1;
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cat2 = #1 1;
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cat3 = #1 1;
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cat4 = #1 1;
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foo1 = #1 1;
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foo2 = #1 1;
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foo3 = #1 1;
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foo4 = #1 1;
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bar1 <= #1 1;
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bar2 <= #1 1;
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bar3 <= #1 1;
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bar4 <= #1 1;
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end
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always @(cat1)
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$write("time=%0t, cat1=%0h\n", $time, cat1);
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always @(cat2) $write("time=%04d, cat2=%0h\n", $time, cat2);
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always @(cat3) $write("time=%04d, cat3=%0h\n", $time, cat3);
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always @(cat4) $write("time=%04d, cat4=%0h\n", $time, cat4);
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always @(foo1) $write("time=%04d, foo1=%0h\n", $time, foo1);
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always @(foo2) $write("time=%04d, foo2=%0h\n", $time, foo2);
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always @(foo3) $write("time=%04d, foo3=%0h\n", $time, foo3);
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always @(foo4) $write("time=%04d, foo4=%0h\n", $time, foo4);
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always @(bar1) $write("time=%04d, bar1=%0h\n", $time, bar1);
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always @(bar2) $write("time=%04d, bar2=%0h\n", $time, bar2);
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always @(bar3) $write("time=%04d, bar3=%0h\n", $time, bar3);
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always @(bar4) $write("time=%04d, bar4=%0h\n", $time, bar4);
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endmodule
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