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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 01:33:07 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
47 lines
1.1 KiB
Verilog
47 lines
1.1 KiB
Verilog
/*
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* This module demonstrates the ability to use a defparam to control
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* the instantation of an instance array, and to also control
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* parameter values within the instance array.
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*/
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module main;
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localparam wid = 5;
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reg [wid-1:0] clk;
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dut xx (.clk(clk));
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// This defparam sets the desired with of the U instance vector.
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defparam main.xx.wid = wid;
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// These defparams set parameters within U instances.
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defparam main.xx.sub[0].U.number = 0;
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defparam main.xx.sub[1].U.number = 1;
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defparam main.xx.sub[2].U.number = 2;
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defparam main.xx.sub[3].U.number = 3;
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defparam main.xx.sub[4].U.number = 4;
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initial begin
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clk = 0;
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#1 clk = 1;
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while (clk != 0)
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#1 clk = clk << 1;
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$finish(0);
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end
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endmodule // main
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module dut #(parameter wid = 1) (input [wid-1:0] clk);
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genvar i;
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for (i = 0 ; i < wid ; i = i+1) begin : sub
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target U (.clk(clk[i]));
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end
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endmodule //
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module target(input wire clk);
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parameter number = 999;
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always @(posedge clk)
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$display("%m: number=%0d", number);
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endmodule // target
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