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21 lines
244 B
Verilog
21 lines
244 B
Verilog
module test();
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localparam w = 8;
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task t;
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reg [w:1] v;
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localparam w = 2;
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begin
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v = 8'hAA;
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$display("%b", v);
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if (v === 8'hAA)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endtask;
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initial t;
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endmodule
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