mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-02 22:48:43 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
44 lines
881 B
Verilog
44 lines
881 B
Verilog
// Check variable initialisation in constant functions.
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module constfunc8();
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function real uninitialised_r(input dummy);
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real value;
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uninitialised_r = value;
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endfunction
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function [7:0] uninitialised_2(input dummy);
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reg bool [5:0] value;
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uninitialised_2 = {1'b1, value, 1'b1};
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endfunction
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function [7:0] uninitialised_4(input dummy);
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reg [5:0] value;
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uninitialised_4 = {1'b1, value, 1'b1};
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endfunction
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localparam result_r = uninitialised_r(0);
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localparam result_2 = uninitialised_2(0);
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localparam result_4 = uninitialised_4(0);
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reg failed;
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initial begin
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failed = 0;
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$display("%0g", result_r);
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if (result_r != 0.0) failed = 1;
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$display("%b", result_2);
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if (result_2 !== 8'b10000001) failed = 1;
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$display("%b", result_4);
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if (result_4 !== 8'b1xxxxxx1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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