mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 03:43:19 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
61 lines
1.4 KiB
Verilog
61 lines
1.4 KiB
Verilog
// Test system function calls in constant functions
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module constfunc6();
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function signed [7:0] abs_i(input signed [7:0] a);
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abs_i = $abs(a);
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endfunction
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function real abs_r(input real a);
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abs_r = $abs(a);
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endfunction
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function [7:0] min_i(input [7:0] a, input [7:0] b);
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min_i = $min(a, b);
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endfunction
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function [7:0] max_i(input [7:0] a, input [7:0] b);
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max_i = $max(a, b);
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endfunction
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function real min_r(input real a, input real b);
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min_r = $min(a, b);
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endfunction
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function real max_r(input real a, input real b);
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max_r = $max(a, b);
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endfunction
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localparam [7:0] absIResult = abs_i(-25);
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localparam [7:0] minIResult = min_i(25, 30);
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localparam [7:0] maxIResult = max_i(25, 30);
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localparam real absRResult = abs_r(-25.0);
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localparam real minRResult = min_r(25.0, 30.0);
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localparam real maxRResult = max_r(25.0, 30.0);
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reg failed;
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initial begin
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failed = 0;
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$display("%0d", absIResult);
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$display("%0g", absRResult);
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$display("%0d", minIResult);
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$display("%0g", minRResult);
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$display("%0d", maxIResult);
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$display("%0g", maxRResult);
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if ( absIResult !== 8'd25) failed = 1;
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if ( absRResult != 25.0) failed = 1;
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if ( minIResult !== 8'd25) failed = 1;
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if ( minRResult != 25.0) failed = 1;
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if ( maxIResult !== 8'd30) failed = 1;
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if ( maxRResult != 30.0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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