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https://github.com/steveicarus/iverilog.git
synced 2026-09-02 23:38:58 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
// Test system function calls in constant functions
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module constfunc6();
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function [7:0] clog2(input [7:0] a);
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clog2 = $clog2(a);
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endfunction
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function real log10(input [7:0] a);
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log10 = $log10(a);
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endfunction
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function real sqrt(input real a);
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sqrt = $sqrt(a);
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endfunction
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function real pow_i(input [7:0] a, input [7:0] b);
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pow_i = $pow(a, b);
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endfunction
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function real pow_r(input real a, input real b);
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pow_r = $pow(a, b);
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endfunction
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localparam [7:0] clog2Result = clog2(25);
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localparam real log10Result = log10(100);
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localparam real sqrtResult = sqrt(25.0);
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localparam [7:0] powIResult = pow_i(4, 3);
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localparam real powRResult = pow_r(4.0, 3.0);
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reg failed;
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initial begin
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failed = 0;
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$display("%0d", clog2Result);
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$display("%0g", log10Result);
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$display("%0g", sqrtResult);
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$display("%0d", powIResult);
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$display("%0g", powRResult);
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if (clog2Result !== 8'd5) failed = 1;
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if (log10Result != 2.0) failed = 1;
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if ( sqrtResult != 5.0) failed = 1;
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if ( powIResult !== 8'd64) failed = 1;
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if ( powRResult != 64.0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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