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By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
69 lines
1.3 KiB
Verilog
69 lines
1.3 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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// Test array variables inside a constant function
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module constfunc14();
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function [7:0] concat1(input [7:0] value);
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reg [3:0] tmp[1:2];
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begin
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{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
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{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
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end
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endfunction
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function [7:0] concat2(input [7:0] value);
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reg [3:0] tmp[1:2];
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begin
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
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{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
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`else
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{tmp[1]} = {value[3:0]};
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{concat2[3:0], concat2[7:4]} = {4'bxxxx, tmp[1]};
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`endif
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end
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endfunction
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function [7:0] concat3(input [7:0] value);
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reg [3:0] tmp[1:2];
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begin
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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{tmp['bx], tmp[1]} = {value[3:0], value[7:4]};
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{concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]};
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`else
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{tmp[1]} = {value[7:4]};
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{concat3[3:0], concat3[7:4]} = {4'bxxxx, tmp[1]};
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`endif
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end
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endfunction
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localparam res1 = concat1(8'ha5);
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localparam res2 = concat2(8'ha5);
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localparam res3 = concat2(8'ha5);
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reg failed = 0;
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initial begin
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$display("%h", res1); if (res1 !== 8'h5a) failed = 1;
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$display("%h", res2); if (res2 !== 8'h5x) failed = 1;
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$display("%h", res3); if (res3 !== 8'h5x) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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