mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-02 22:48:43 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
54 lines
1000 B
Verilog
54 lines
1000 B
Verilog
module constfunc1();
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function integer median;
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input integer a;
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input integer b;
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input integer c;
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begin
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if (a < b)
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begin
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if (a < c)
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median = (b < c) ? b : c;
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else
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median = a;
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end
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else
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begin
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if (a < c)
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median = a;
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else
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median = (b < c) ? c : b;
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end
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end
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endfunction
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localparam value1 = median(1, 2, 3);
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localparam value2 = median(1, 3, 2);
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localparam value3 = median(2, 1, 3);
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localparam value4 = median(2, 3, 1);
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localparam value5 = median(3, 1, 2);
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localparam value6 = median(3, 2, 1);
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initial begin
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$display("value 1 = %0d", value1);
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$display("value 2 = %0d", value2);
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$display("value 3 = %0d", value3);
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$display("value 4 = %0d", value4);
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$display("value 5 = %0d", value5);
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$display("value 6 = %0d", value6);
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if ((value1 === 2)
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&& (value2 === 2)
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&& (value3 === 2)
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&& (value4 === 2)
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&& (value5 === 2)
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&& (value6 === 2))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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