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https://github.com/steveicarus/iverilog.git
synced 2026-09-08 12:23:32 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
53 lines
813 B
Verilog
53 lines
813 B
Verilog
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module test
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(output reg [1:0] foo,
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input wire foo_en1, foo_en2
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/* */);
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always @* begin
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foo = 0;
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case (1'b1)
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foo_en1 : foo = 1;
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foo_en2 : foo = 2;
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endcase
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end
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endmodule // test
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module main;
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wire [1:0] foo;
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reg foo_en1, foo_en2;
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test dut (.foo(foo), .foo_en1(foo_en1), .foo_en2(foo_en2));
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task fail;
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begin
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$display("FAILED -- foo=%b, foo_en1=%b, foo_en2=%b",
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foo, foo_en1, foo_en2);
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$finish;
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end
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endtask // fail
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initial begin
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foo_en1 = 0;
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foo_en2 = 0;
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#1 if (foo !== 2'd0)
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fail;
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foo_en2 = 1;
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#1 if (foo !== 2'd2)
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fail;
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foo_en1 = 1;
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#1 if (foo !== 2'd1)
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fail;
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foo_en2 = 0;
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#1 if (foo !== 2'd1)
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fail;
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$display("PASSED");
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end // initial begin
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endmodule // main
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