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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
46 lines
1015 B
Verilog
46 lines
1015 B
Verilog
`begin_keywords "1364-2005"
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/*
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* This tests the synthesis of a case statement that has an empty case.
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*/
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module main;
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reg bit, foo, bar;
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// Combinational device that sends 1 or 0 to foo, to follow bit.
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// This tests the special situation that the case condition only sets
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// some of the bits that the case as a whole sets. This is OK if
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// the bits that are sometimes not set are covered elsewhere.
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always @*
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begin
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foo = 0;
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bar = 0;
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case (bit)
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1'b0: bar = 1;
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1'b1: foo = 1;
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endcase // case(bit)
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end
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(* ivl_synthesis_off *)
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initial begin
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bit = 0;
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# 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
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if (bit !== 0 || foo !== 0 || bar !== 1) begin
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$display("FAILED");
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$finish;
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end
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bit <= 1;
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#10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
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if (bit !== 1 || foo !== 1 || bar !== 0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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`end_keywords
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