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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
/*
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* This tests the synthesis of a very sparse case statement. The
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* combinational case statement below specifies only two of 256
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* possible selections, with all the remaining left to the default.
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* What's more, all the inputs to the MUX are constant, giving
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* even further opportunity for optimization.
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*/
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module main;
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reg [7:0] val;
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reg [7:0] out;
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(* ivl_combinational *)
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always @ (val) begin
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case (val)
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8'h2a: out = 8'h40 ;
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8'h1f: out = 8'h20 ;
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default: out = 8'h04 ;
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endcase
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end
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integer idx;
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(* ivl_synthesis_off *) initial begin
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for (idx = 0 ; idx < 256 ; idx = idx + 1) begin
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val <= idx;
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#1 ;
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if (val == 8'h2a) begin
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if (out !== 8'h40) begin
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$display("FAILED -- val=%h, out=%h (%b)", val, out, out);
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$finish;
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end
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end else if (val == 8'h1f) begin
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if (out !== 8'h20) begin
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$display("FAILED -- val=%h, out=%h (%b)", val, out, out);
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$finish;
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end
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end else if (out !== 8'h04) begin
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$display("FAILED -- val=%h, out=%h (%b)", val, out, out);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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