mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 19:56:53 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
74 lines
2.0 KiB
Verilog
74 lines
2.0 KiB
Verilog
`timescale 1ns/100ps
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module top;
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reg pass = 1'b1;
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integer idelay = 2;
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real rdelay = 2.0;
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real rin = 1.0;
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reg ctl = 1'b1;
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wire outr, outi, muxr, muxi;
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wire real rout;
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reg in = 1'b1;
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assign #(idelay) outi = in;
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assign #(rdelay) outr = ~in;
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assign #(rdelay) rout = rin;
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assign #(idelay) muxi = ctl ? in : 1'b0;
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assign #(rdelay) muxr = ctl ? ~in : 1'b1;
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initial begin
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// Wait for everything to settle including the delay value!
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#2.1;
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if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin
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$display("FAILED: initial value, expected 1'b1/1'b0/1.0, got %b/%b/%f",
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outi, outr, rout);
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pass = 1'b0;
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end
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if (muxi !== 1'b1 || muxr !== 1'b0) begin
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$display("FAILED: initial value (mux), expected 1'b1/1'b0, got %b/%b",
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muxi, muxr);
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pass = 1'b0;
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end
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in = 1'b0;
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rin = 2.0;
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#1.9;
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if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin
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$display("FAILED: mid value, expected 1'b1/1'b0/1.0, got %b/%b/%f",
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outi, outr, rout);
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pass = 1'b0;
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end
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if (muxi !== 1'b1 || muxr !== 1'b0) begin
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$display("FAILED: mid value (mux), expected 1'b1/1'b0, got %b/%b",
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muxi, muxr);
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pass = 1'b0;
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end
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#0.2;
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if (outi !== 1'b0 || outr !== 1'b1 || rout != 2.0) begin
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$display("FAILED: final value, expected 1'b0/1'b1/2.0, got %b/%b/%f",
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outi, outr, rout);
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pass = 1'b0;
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end
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if (muxi !== 1'b0 || muxr !== 1'b1) begin
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$display("FAILED: final value (mux), expected 1'b0/1'b1, got %b/%b",
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muxi, muxr);
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pass = 1'b0;
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end
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idelay = 3;
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in = 1'b1;
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#2.9;
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if (outi !== 1'b0) begin
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$display("FAILED: initial change, expected 1'b0, got %b", outi);
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pass = 1'b0;
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end
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#0.2;
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if (outi !== 1'b1) begin
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$display("FAILED: initial change, expected 1'b1, got %b", outi);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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