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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
18 lines
277 B
Verilog
18 lines
277 B
Verilog
`timescale 1ns/1ns
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module top;
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reg itrig = 1'b0;
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wire [31:0] tm, stm;
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assign tm = itrig * $time;
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assign stm = itrig * $stime;
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initial begin
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$monitor(tm,, stm);
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#1 itrig = 1'b1;
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#1 itrig = 1'b0;
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#1 itrig = 1'b1;
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#1 itrig = 1'b0;
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end
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endmodule
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