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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:03:32 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
53 lines
1.0 KiB
Verilog
53 lines
1.0 KiB
Verilog
module top;
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reg pass;
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reg in;
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wire ca;
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assign ca = in;
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initial begin
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pass = 1'b1;
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if (ca !== 1'bx || in !== 1'bx) begin
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$display("Failed T0 check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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in = 1'b0;
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#1;
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if (ca !== 1'b0 || in !== 1'b0) begin
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$display("Failed 0 check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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in = 1'b1;
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#1;
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if (ca !== 1'b1 || in !== 1'b1) begin
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$display("Failed 1 check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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force ca = 1'b0;
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#1;
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if (ca !== 1'b0 || in !== 1'b1) begin
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$display("Failed force 0 check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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in = 1'bx;
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#1;
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if (ca !== 1'b0 || in !== 1'bx) begin
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$display("Failed change a check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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force ca = 1'b1;
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#1;
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if (ca !== 1'b1 || in !== 1'bx) begin
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$display("Failed force 1 check, in %b, ca %b", in, ca);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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