mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-05 00:51:28 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
76 lines
1.4 KiB
Verilog
76 lines
1.4 KiB
Verilog
/*
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* Verify that the continuous assignments support a delay that is
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* greater than 32 bits. The top delays are in seconds and the other
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* delays are in ps. The second delays all require more than 32 bits
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* to work correctly. They will use the /d version.
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*/
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`timescale 1s/1s
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module gt32b;
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wire real rlval;
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wire rval;
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wire aval[1:0];
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wire [7:0] psval;
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assign #1 rlval = 1.0;
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assign #2 rval = 1'b1;
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assign #3 aval[0] = 1'b0;
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assign #4 psval[1] = 1'b1;
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initial begin
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$timeformat(-12, 0, " ps", 16);
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#1;
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$display("dl:gt32b- %t", $realtime);
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end
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always @(rlval) begin
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$display("rl:gt32b- %t", $realtime);
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end
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always @(rval) begin
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$display("rg:gt32b- %t", $realtime);
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end
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always @(aval[0]) begin
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$display("ar:gt32b- %t", $realtime);
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end
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always @(psval) begin
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$display("ps:gt32b- %t", $realtime);
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end
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endmodule
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`timescale 1ps/1ps
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module ls32b;
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wire real rlval;
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wire rval;
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wire aval[1:0];
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wire [7:0] psval;
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assign #1 rlval = 1.0;
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assign #2 rval = 1'b1;
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assign #3 aval[0] = 1'b0;
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assign #4 psval[1] = 1'b1;
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initial begin
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#1;
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$display("dl:ls32b- %t", $realtime);
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end
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always @(rlval) begin
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$display("rl:ls32b- %t", $realtime);
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end
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always @(rval) begin
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$display("rg:ls32b- %t", $realtime);
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end
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always @(aval[0]) begin
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$display("ar:ls32b- %t", $realtime);
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end
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always @(psval) begin
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$display("ps:ls32b- %t", $realtime);
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end
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endmodule
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