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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
92 lines
2.2 KiB
Verilog
92 lines
2.2 KiB
Verilog
// Copyright (c) 2000 Stephen Williams ([email protected])
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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/*
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* This module implements what essentially amounts to an array of DFF
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* devices with output enable. This test checks the operation of the
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* bufif0 and bufif1 devices.
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*/
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module grayGap (ad, clk, read, write);
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output [31:0] ad;
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input clk, read, write;
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reg [15:0] regff;
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bufif0 ad_drv [31:0] (ad, {16'b0, regff}, read);
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always @(posedge clk)
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if (write) regff = ad[15:0];
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endmodule
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module main;
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wire [31:0] ad;
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reg clk, read, write;
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reg [31:0] ad_val;
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reg ad_en;
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bufif1 ad_drv[31:0] (ad, ad_val, ad_en);
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grayGap test (ad, clk, read, write);
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always #10 clk = ~clk;
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initial begin
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clk = 1;
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read = 1;
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write = 0;
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$monitor($time, "ad=%b", ad);
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// Set up to write a value into the grayGap register.
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@(negedge clk)
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ad_val = 32'haaaa_aaaa;
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read = 1;
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write = 1;
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ad_en = 1;
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// The posedge has passed, now set up to read that value
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// out. Turn all the drivers off for a moment, to see that the
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// line becomes tri-state...
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@(negedge clk)
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ad_en = 0;
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write = 0;
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// Now read the value.
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#1 read = 0;
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#1 $display("Wrote %h, got %h", ad_val, ad);
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if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin
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$display("FAILED -- ad is %b", ad);
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$finish;
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end
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#2 read = 1;
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$display("PASSED");
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$finish;
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end
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endmodule // main
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