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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 01:13:47 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
42 lines
919 B
Verilog
42 lines
919 B
Verilog
module top;
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reg pass = 1'b1;
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integer count;
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reg clk = 0, in = 0;
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reg result;
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always #10 clk = ~clk;
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always #20 in = ~in;
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initial begin
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count = 3;
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result = repeat(count) @(posedge clk) in;
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if ($simtime != 30 && result != 1'b0) begin
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$display("Failed blocking repeat(3) at %0t, expected 1'b0, got %b",
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$simtime, result);
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pass = 1'b0;
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end
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#15;
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count = 0;
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result = repeat(count) @(posedge clk) in;
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if ($simtime != 45 && result != 1'b1) begin
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$display("Failed blocking repeat(0) at %0t, expected 1'b1, got %b",
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$simtime, result);
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pass = 1'b0;
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end
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#20;
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count = -1;
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result = repeat(count) @(posedge clk) in;
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if ($simtime != 55 && result != 1'b0) begin
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$display("Failed blocking repeat(0) at %0t, expected 1'b0, got %b",
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$simtime, result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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endmodule
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