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Lars-Peter Clausen
708f7bc651
Check that for array identifiers $bits() includes the total size of the signal. Signed-off-by: Lars-Peter Clausen <[email protected]>
38 lines
829 B
Verilog
38 lines
829 B
Verilog
// Check that passing a array identifiers and array slices to $bits works as expected
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module test;
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bit failed = 1'b0;
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`define check(expr, value) do begin \
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if ($bits(expr) !== value) begin \
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$display("FAILED(%d): $bits(", `"expr`", ") is %0d", `__LINE__, $bits(expr), " expected %0d", value); \
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failed = 1'b1; \
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end \
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end while (0)
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typedef bit T[3:0];
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T x;
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byte y[7:0][2:0];
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initial begin
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integer i;
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i = 4;
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`check(x, 4);
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`check(y, $bits(byte) * 3 * 8);
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`check(y[0], $bits(byte) * 3);
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`check(y[1:0], $bits(byte) * 3 * 2);
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`check(y[1+:3], $bits(byte) * 3 * 3);
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`check(y[4-:4], $bits(byte) * 3 * 4);
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`check(y[i-:2], $bits(byte) * 3 * 2);
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`check(y[i+:2], $bits(byte) * 3 * 2);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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