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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
35 lines
601 B
Verilog
35 lines
601 B
Verilog
module main;
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reg foo_reg;
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byte foo_byte;
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int foo_int;
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shortint foo_shortint;
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longint foo_longint;
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initial begin
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if ($bits(foo_reg) != 1) begin
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$display("FAILED");
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$finish;
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end
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if ($bits(foo_byte) != 8) begin
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$display("FAILED");
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$finish;
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end
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if ($bits(foo_int) != 32) begin
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$display("FAILED");
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$finish;
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end
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if ($bits(foo_shortint) != 16) begin
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$display("FAILED");
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$finish;
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end
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if ($bits(foo_longint) != 64) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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