mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 07:43:07 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
15 lines
278 B
Verilog
15 lines
278 B
Verilog
// Check behaviour with variable array indices on LHS of procedural
|
|
// continuous (reg) assignment. This should be rejected by the compiler.
|
|
module top;
|
|
|
|
reg array1[2:1];
|
|
|
|
integer index = 1;
|
|
|
|
initial begin
|
|
assign array1[index] = 1'b1;
|
|
deassign array1[index];
|
|
end
|
|
|
|
endmodule
|