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Lars-Peter Clausen
ea57b6dd9a
Check that using a real valued expression as an array index is rejected during elaboration. Signed-off-by: Lars-Peter Clausen <[email protected]>
13 lines
162 B
Verilog
13 lines
162 B
Verilog
// Check that real expressions can not be used as array indices.
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module test;
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reg [1:0] a[1:0];
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real r;
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initial begin
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a[r] = 2'b10;
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end
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endmodule
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