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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
33 lines
816 B
Verilog
33 lines
816 B
Verilog
// This test was written to catch spurious "internal error" messages generated
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// by the compiler, so uses a gold file for checking.
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module test();
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reg [7:0] Reg[0:3];
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reg [7:0] Val0 = 255;
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reg [7:0] Val1 = 1;
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reg [7:0] Val2 = 2;
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reg [7:0] Val3 = 3;
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always @* begin
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Reg[0] = Val0;
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Reg[1] = Val1;
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Reg[2] = Val2;
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Reg[3] = Val3;
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end
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initial begin
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Val0 <= 0; // To make sure this triggers at T0 for SystemVerilog
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#1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]);
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Val0 = 4;
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#1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]);
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Val1 = 5;
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#1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]);
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Val2 = 6;
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#1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]);
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Val3 = 7;
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#1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]);
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end
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endmodule
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