mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-02 10:37:53 +02:00
Lars-Peter Clausen
338516bc55
Check that constant recursive functions are supported. Check both Verilog style using assignments to the implicit function return signal and SystemVerilog style using `return`. Signed-off-by: Lars-Peter Clausen <[email protected]>
4 lines
51 B
Plaintext
4 lines
51 B
Plaintext
factorial 3 = 6
|
|
factorial 4 = 24
|
|
factorial 5 = 120
|